blit instruction

for memcpy, memmove, etc

some design choices:

  • the instruction could be restricted to sizes known statically
  • blit lowering could involve unaligned loads/stores; what are the tradeoffs there?
  • support or not of overlapping memory areas

some silly and not so silly challenges:

  • the blit instruction will take at least 3 arguments (two addresses and one size), this means that internally it will have to be split (like calls); it may be time to have a principled handling of these instruction blocks, let's see how the implementation unfolds
  • the blit instruction needs to be taken care of early in the load optimization (it is a new kind of memory write!)
  • the blit instruction should be modeled faithfully in the load optimization
Assigned to
2 years ago
2 years ago

~mpu 2 years ago*

[moved in description]

~sircmpwn 2 years ago

the instruction could be restricted to sizes known statically

Why? That would reduce its utility by a lot and I don't think it's actually necessary for the implementation.

Another note is that the differences between memcpy and memmove will have design consequences.

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