Hi! I’m currently a PhD student in the Circuits and Systems group at Imperial College London, supervised by John Wickerson.
My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs). An implementation in the Coq theorem prover called Vericert can be found on Github.
I have also worked on random testing for FPGA synthesis tools. Verismith is a fuzzer that will randomly generate a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output to the input. If these differ, the design is automatically reduced until the bug is located.
Movement inside of Org can be improved in several ways.
There is currently no way of going directly to an ID, because they are in different files. It would be useful to automatically resolve the number at the front to the file that they will be in.
Once that is implemented, a way to easily navigate backlinks could also be added, because in the exporting function there is now a way to get the title and ID of the backlinks.